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Johannes,
What would be the benefit of running the design at 120Mhz instead of 60Mhz? I understand that this may reduce area using resource sharing... is there anything else?
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For the number of clock domains in your design their is a simple rule of thumb: the less the easier! As your input clock is 120MHz you can run the whole design at that speed with clock enables for the 60 and 20MHz. On the downside is that you then overconstrain the 20 and 60MHz part. It is a design=tradeoff.
I would advice you to get some feeling with fpga's first: try to do a simple adder, multiplier, mac and see how it is implemented, how many cells it takes what the maximum speed is etc... Take extreme care if you start with devisions, modulos or sqrt, they are totally not efficient to implement...
Good luck
Honored Contributor
