Upsample/Downsample timing constraining

Pipelining has no rule of thumb but I prefer to add registers every two or so logic levels for a high speed design.

You cannot I believe pipeline internal logic of inferred adders or multipliers.

Adders are made from fabric logic. Multipliers hopefully from dedicated blocks.

So you better instantiate adders with good pipeline.

To add registers to mult outputs, you can do that directly in your code or schematic i.e. don't take mult outputs to logic directly but through one stage registers.

If your address changes every 3 clocks then you got useful candidate for a multicycle of 3 on address registers.