Honored Contributor
Honored ContributorThe notion of clock enable is indeed my choice but since your two clocks are in phase(and related from same PLL) then it should be ok. I am not clear about multicycle issue and it is one thing that I don't want to play with unless absolutely sure. Your timing violations seem more severe than tackling it with multicycles.
Few things I can suggest. - Identify which paths are failing - Your addressing must be pipelined if it takes long paths. - add fabric registers to your multiplier outputs(apart from dedicated block registers). I find this very useful to shorten routing. - adders should pipelined internally and at outputs. as a side note: I am not clear about one functional issue. your upsampler inserts two zeros after each sample thus the data rate becomes 60Msps yet you write it to RAM at 20Msps. May be you have set your RAM to all zeros then you just write data implying that RAM is implementing the zero insertion rather than the upsampler?
