Upsample/Downsample timing constraining

Dear,

My approach would be to tackle such a problem: run the whole design at 60 (or even 120)MHz and use a clockenable to get an effective data rate of 20 or 60MHz. This will make all (hard) cross clock domain timing issues disappear. Functional simulation will automatically match the real world system.

If you want to stick with the multi clock design all clocks have to come from the same oscillator. The settings to do are explained in the Q2 handbook chapter 7 : http://www.altera.com/literature/hb/qts/qts_qii53018.pdf page 7-47

About the huge 100ns negative slack: did you pipeline the system?