Upsample/Downsample timing constraining

Thanks for answering Mr. Kaz,

I will try to clarify the design as much as possible but let me know if additional information is needed.

I am targeting EP3C120F780. I am using the simulink coder instead of dsp builder, which generates generic target independent and not that optimized rtl code.

The design has 28 lvds inputs running at 120Mhz (20Msps with 12 bits deser ratio). The deserializer module is manually implemented as per FvM suggestions in forums posts. One PLL generates all the clock for this part of the system.

All channels data is scaled with a multi-channel multiplier and then up-sampled (output is equal to the input one every N rising edges) in my case N is 3. The output of the up-sampler is: sample(1), 0, 0, sample(2), 0, 0, sample(3) and so on.

Each channel has a ram memory whose address are calculated on the fly at 20Mhz ( clk[2] ). The addresses are changed every 3 clock edges matching the up-sampling process.

At every rising edge of the 60Mhz clock, the ram has an output, all the data is summed up giving one output channel and goes into 60 tap fir filter. Then the down-sample process takes one sample out of 3 in time.

The addresses need a lot of calculations that have not been pipelined still.

In the case of the upsampler, the lanch clock is 20Mhz and the latch one is 60Mhz. In the case of the down sampling, the lanch clock is 60Mhz and the latch one is 20Mhz.

Hope there is a better understanding of my system now. In case not, please let me know how can I present a better question to the forum.

Thanks again