Upsample/Downsample timing constraining

It sounds odd to me that you can't pass timing for 60MHz clock which is way too slow for most modern devices. It is also hard to advise on constraints when your design is unknown. the slack of -100ns is astronomically bad. You better describe to the forum your clocking scheme carefully. One last thing if you use dspbuilder then you shouldn't worry about sdc as it takes over from you.