SMoor12
New Contributor
New ContributorUpgraded to Quartus Pro 22.1: "No key to decrypt data block" error for Low Latency 100G Ethernet
We've upgraded from Quartus Pro 19.2 to 22.1. A previously working Stratix 10SX project using the Low Latency 100G Ethernet IP now fails to compile with:
Error(13223): Verilog HDL or VHDL er...
We managed to resolve this problem, and it turned out it wasn't a licensing issue.
The issue was that IP upgrade tool from Quartus Pro 19.2 to 22.1 didn't work. Presumably the tool left behind Verilog that was encrypted with the keys of 19.2. Deleting the IP core from the design and adding a new IP core from 22.1 with the same configuration parameters did achieve a design that built successfully.
