Up-down counters

Edit:

I wrote this post before catching up with Batfink's above post. There is plenty of similarity.

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Hi,

I'm new to VHDL..

i'm creating the up-down counter with async rst and a load enable signal.

this load enable will determine any number within the range to be entered into the counter whereas the reset signal will reset the counter to the value of the number loaded..my problem is i didn't get the output.

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You should say:

i'm creating the up-down counter with async rst and sync load enable signal.this load enable will determine any number within the range to be entered into the counter whereas the reset signal will reset the counter to zero.

Try this untested code:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity cnt is

port (

CLK : in std_logic;

RST : in std_logic;

LE : in std_logic;

UD : in std_logic;

D : in std_logic_vector(3 downto 0);

Q : out std_logic_vector(3 downto 0)

);

end cnt;

architecture beh of cnt is

signal Q_IN : unsigned(3 downto 0);

begin

Q <= std_logic_vector(Q_IN);

process( RST, CLK)

begin

if RST = '1' then

Q_IN <= "0000";

elsif CLK='1' and CLK'event then

if LE = '1' then

Q_IN <= D;

elsif UD = '1' then

Q_IN <= Q_IN + 1;

else

Q_IN <= Q_IN - 1;

end if;

end if;

end process;

end beh;