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Altera_Forum
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11 years ago

up down counter problem

hi everyone i try to make a project to count people entering or going out from a hall using VHDL and altera board DE0 i made two clocks one for counting up (clku) it come from a trigger outs...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

As the signals are asynchronous (external to the board) they need to pass each a double FF synchronizer before entering the edge detection. Otherwise you should expect a certain amount of counting errors (missed or double counted events).