up down counter problem

First: Please use the CODE-Tags for Code. (obvious, isn't it?)

ENTITY mod_ten_ud ISPORT(
clku,clkd, enable :IN BIT ;
q :OUT INTEGER RANGE 0 TO 9);END mod_ten_ud;
ARCHITECTURE a OF mod_ten_ud
ISBEGIN
PROCESS (clku ,clkd)
VARIABLE count :INTEGER RANGE 0 TO 9;
BEGIN
IFenable = '1'
THEN
IF( clku = '1' AND clku'EVENT )
THEN count := count + 1;
ELSIF( clkd = '1' AND clkd'EVENT )
THEN count := count - 1;
END IF;
END IF;
q <= count;
END PROCESS;
END a;

Second: You can't use two clock edges in one process. And it is rather bad style to declare a simple signal as clock and count on the clock edges.

Better is:

You create one very fast clock to sample your two input signals. Like this:

if (rising_edge(fast_clk)) then
   prev_sig1   <= sig1;
   prev_sig2   <= sig2;
   if ((prev_sig1 = '0') and (sig1 = '1')) then
      {count up}
   end if;
   if ((prev_sig2 = '0') and (sig2 = '1')) then
      {count down}
   end if;
end if;

This will also give you something like an edge-detect on your signals. But without the meaning that these are clocks.