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Altera_Forum's avatar
Altera_Forum
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9 years ago

up counter needs fixing - confused . simple question

Hi, this is a simple counter with asynch pre-set(not wired in diagram), enable, load and synch add +1. i can't figure the trick to get rid of one extra mux column and use the FF enable (where red arr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Assuming you have connected the FPGA to the board as per the instructions in the data sheet with the correct Vcc and Ground Pins, then current draw wont be a worry as it will always be within the spec on the datasheet.

There is a power analysis tool that can run your design through to give estimated power draw for your design, but that may be a bit advanced for what you are doing.

Just be assured that if the design fits in the device and meets timing (and you have designed it to correct correctly with the connected IOs) then it will work.