Unsigned to signed conversion and its simulation in Modelsim

This works for me after making one correction unrelated to the signed issue. data_out needs to be a variable in order to make procedural assignments to it. You have it declared as a wire. (you are also using Verilog-1995 style ports, which I updated)

module signed_unsigned (
  input logic sign,
  input logic clk,
  input unsigned  data_in,
  output logic signed  data_out
);
  always_ff @ (posedge clk) begin
  if (sign)
    data_out <= -data_in;
  else
    data_out <= data_in;
  end
endmodule

module top;
   bit clk, sign;
      logic unsigned  data_in;
   logic signed  data_out;
 
  always# 5 clk++;
   
  initial begin
      sign=1;
      data_in = 8'hff;
   @(negedge clk)
     $displayh(data_in,,data_out);
      data_in = 8'hAA;
   @(negedge clk)
      $displayh(data_in,,data_out);
     sign=0;
      data_in = 8'hff;
   @(negedge clk)
     $displayh(data_in,,data_out);
      data_in = 8'hAA;
   @(negedge clk)
      $displayh(data_in,,data_out);
     $finish;      
end
   signed_unsigned su(.*);
   
endmodule : top

# Loading work.top(fast)
#  run -all
#  ff 101
#  aa 156
#  ff 0ff
#  aa 0aa
#  ** Note: $finish    : signed.sv(25)