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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Univercity program VWF simulation error

I try to simulate Generic parity detector example in the book Circuit Design with VHDL. (Velnei A. Pedroni). But, simulation waveform editor gives an error. My synthesis editor is Quartus 2 web editi...
JJame3's avatar
JJame3
Icon for New Contributor rankNew Contributor
7 years ago

For what it's worth, the VWF simulator gave me only flatline outputs in the generated VWF file, even on the simplest possible logic. (I saw no error message appear, though). This persisted from the first time I tried it after installing Quartus Prime 18.0 Lite. However, once I restored defaults as indicated in the prior posting, simulation started working properly.

Thanks.