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I am trying to migrate usb design from xilinx virtex V based fpga to Altera cyclone III. The usb implementation is written in VHDL and uses a few asynchronous ram constructs. (synchronous write but asynchronous read).
Quartus II v9. gives uninferred ram logic info
Info: RAM logic "usb_controller_interface:usb_cntrlr_intfc_inst|usb_controller:usb_controller_inst|pkt_handler:pkt_handler_inst|rx_handler:Inst_rx_handler|rx_controller:rx_controller_inst|stream_ep_flag_handler:stream_ep_flag_handler_inst|out_buf_length" is uninferred due to inappropriate RAM size
what does it imply?
1) will my ram logic not be implemented or it will be implemented in logic cells rather than m9k memory blocks.
2)when i use attribute ramstyle = "logic , no_rw_check" the above info persists.
3)when ramstyle is changed to "MLAB , no_rw_check" memory bits usage is increased and logic elements usage decreases. quartus deduces "altdpram".
since "altdpram" is not supported in cyclone III neither is MLAB so it offers equivalent solution with relevant warnings.
is there any other way to implement asynchronous ram in cyclone III?
Thanks and regards.
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Hi,
1. The memory will be implemented in logic cells.
2. As far as I know all RAM's in Cyclone III are synchronous
3. Is that really true, Cyclone III have no MLAB's ( at least as far as I know)
Kind regards
GPK
Honored Contributor
