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AlenaK's avatar
AlenaK
Icon for New Contributor rankNew Contributor
6 years ago

Unexpected transport delays in functional simulation

Hello, we're trying to verify a circuit using Functional Simulation. We know that output signal goes to state '0' at the clock's rising edge. But we see the output switching delay. So, the questi...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

It's unlikely that you're seeing a transport delay when performing a functional simulation. Are you saying the output is going low between the current and next clock edges?

As mentioned, try using the timing analyzer on the output path to see if the design is failing timing.

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