Forum Discussion
AlenaK
New Contributor
New ContributorUnexpected transport delays in functional simulation
Hello, we're trying to verify a circuit using Functional Simulation. We know that output signal goes to state '0' at the clock's rising edge. But we see the output switching delay. So, the questi...
KennyT_altera
Super Contributor
Super ContributorHi Alena,
What device that you were using? timing simulation should be avoided as it take long time. We would suggest to use timing analyzer instead.
