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Altera_Forum
Honored Contributor
13 years agoHere is the part of code. I don't think you can reproduce the issue as it happens sometime during large project build.
signal counter : integer range 0 to 2 := 0;
-- coefficients
type type1 is array(0 to 13) of integer range -2**15-1 to +2**15-1;
constant polyphase1: type1 := (-10,-56,215,-556,1209,-2527,6966,13025,-2559,939,-319,66,16,-27);
constant polyphase2: type1 := (-27,16,66,-319,939,-2559,13025,6966,-2527,1209,-556,215,-56,-10);
constant polyphase3: type1 := (-56,147,-291,474,-662,804,15552,804,-662,474,-291,147,-56,0);
type type2 is array(0 to 13) of std_logic_vector(15 downto 0);
signal coeffs : type2;
....
....
process(reset,clk)
begin
if reset = '1' then
counter <= 0;
elsif rising_edge(clk) then
if counter = 2 then
counter <= 0;
else
counter <= counter + 1;
end if;
for i in 0 to 13 loop
case counter is
when 0 => coeffs(i) <= std_logic_vector(to_signed(polyphase1(i),16));
when 1 => coeffs(i) <= std_logic_vector(to_signed(polyphase2(i),16));
when 2 => coeffs(i) <= std_logic_vector(to_signed(polyphase3(i),16));
when others => null;
end case;
end loop;
end if;
end process;
Thanks P King