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Altera_Forum's avatar
Altera_Forum
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11 years ago

Unexpected latch replacement

Hello,

many forum posts are about unwanted latch inference and related synthesis warnings. Now I that Quartus converts a latch description automatically to a DFF.

I would expect a warning about incomplete sensitivity list, instead Quartus (checked both in V9.0 and V13.1, target is Cyclone III) infers a synchronous register, without a warning or information message.

I must confess, I never noticed this behaviour before. I don't see any related comments in the software handbook, or a synthesis attribute controlling the automatic latch conversion. It doesn't seem to comply with the VHDL LRM at first sight.

Best regards,

Frank 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity lat is
port( 
   enable: in std_logic;
   Output: out std_logic;
   Input: in std_logic);
end;
 
architecture behavioral of lat is
begin
-- input is missing in the sensitivity list, unexpectedly infers a synchronous register
process (enable) is
begin
   if enable = '1' then
      output <= input;
   end if;
end process;
end;

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I sympathesize with the tools here.

    you are saying if enable changes to 1 go...

    if input changes don't...

    so in effect enable acts same as clock and implementation is correct with what you ask for.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    The behaviour is what you would expect in a functional simulation, but not according to hardware synthesis rules. They say you need an edge sensitive expression to infer a FF.

    Compare with VHDL templates

    Positive edge register: 

    -- Update the register output on the clock's rising edge
process (<clock_signal>)
begin
  if (rising_edge(<clock_signal>)) then
    <register_variable> <= <data>;
  end if;
end process;

    Transparent latch 

    -- Update the variable only when updates are enabled
process(<enable>, <data>)
begin
  if (<enable> = '1') then
    <latch_variable> <= <data>;
  end if;
end process;

    The surprizing point is that (in this case) you get a FF (positive edge register) by omitting <data> from the sensitivity list. I would rather expect latch inference with a incomplete sensitivity list warning, as we get it in other cases.