Unexpected latch replacement

The behaviour is what you would expect in a functional simulation, but not according to hardware synthesis rules. They say you need an edge sensitive expression to infer a FF.

Compare with VHDL templates

Positive edge register:

-- Update the register output on the clock's rising edge
process (<clock_signal>)
begin
  if (rising_edge(<clock_signal>)) then
    <register_variable> <= <data>;
  end if;
end process;

Transparent latch

-- Update the variable only when updates are enabled
process(<enable>, <data>)
begin
  if (<enable> = '1') then
    <latch_variable> <= <data>;
  end if;
end process;

The surprizing point is that (in this case) you get a FF (positive edge register) by omitting <data> from the sensitivity list. I would rather expect latch inference with a incomplete sensitivity list warning, as we get it in other cases.