Honored ContributorHi,
On my board, I have a memory connected to FPGA. Currently this memory is used (no logic driving the memory), but the pin assignments are made in QSF and pins declared in top file. Should I ensure to drive appropriate value to these "unused" I/O or would Quartus take care? I suppose, if undriven, it chooses to drive them to VCC/GND, I dont know on what bases. Regards, Satish
Honored ContributorThere's a respective setting in device parameters. I strongly suggest "input with weak pull-up" to avoid collisions, although output driving ground is the default for some (older) logic families.
Honored ContributorHi,
Thanks for your response. I have a question here - though these pins are unused in the sense they dont drive any logic inside or outside the FPGA, their direction is fixed - some pins like WE, CE are outputs, DATA in BiDi and ADDR is again output. So, the "reserve all unused pins" setting in device setting , will it apply to these type of unused pins? Am I missing something? Regards, SatishHonored ContributorI missed the fact, that the pins are declared as ports the top file. In this case, the unused pins setting doesn't apply. You should drive the pins appropriately in your design. You can additionally attach weak pull-up or input hold to input or inout pins in the pin planner, if suitable,
Honored ContributorThanks, but any idea on what bases, Quartus connects such pins to VCC/GND?
Honored ContributorBy default, Quartus will assign any outputs not otherwise defined or connected to Ground (logic 0). Any input that drives no logic will be just a simple input buffer, that has no pull-up unless you define a pull-up/bus hold on that input.
PeteHonored ContributorThanks, but I have an inout pin declared in top file, but not driven, nor is being used inside. For this, the fitter says:
Info: Pin data[..] has a permanently disabled output enable The above is expected. It further says, Warning: Following 90 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results Info: Pin data[..] has VCC driving its datain port Is the above behavior (VCC driving its datain port) expected? Should this not be GND instead, by default?
