Understanding how tool treats HDL code- Verilog blocking and non-blocking assignment

Hello, I am learning Verilog and trying to understand how particular code is synthesized later on.

I understand that blocking statements has a procedural flow as mentioned bellow (ref: asic-world). 1 will execute first, 2 after 1 and 3 at the end.

1 a = b;

2 out_d = 0;

3 {carry, sum} = in + sum_in;

If a bunch of blocking statement are independent of each other (no data dependency) then are they synthesized as a parallel combinational blocks ? As an example the following series of codes don't can be actually execute in parallel in hardware.

1 a[0] = b[0] | b[1]

2 c[0] = b[2] | b[3]

3 d[0] = b[4] | b[5]

Thanks in advance!