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Altera_Forum
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13 years ago

Understanding how tool treats HDL code- Verilog blocking and non-blocking assignment

Hello, I am learning Verilog and trying to understand how particular code is synthesized later on. I understand that blocking statements has a procedural flow as mentioned bellow (ref: asic-wo...
Altera_Forum's avatar
Altera_Forum
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13 years ago

In the case you have asked, they will all generate parrallel hardware.

You shouldnt be thinking about "execution" when it comes to FPGAs - everything you write will be translated to combinatorial logic and registers. So it all depends on context rather than actual code.