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Hi,
I never compare between both Xilinx and Intel product yet.
To be honest I am not familiar with Xilinx product although we are working at same FPGA area.
However, I can lay down another suggestion for you to narrow down this issue.
To map the Xilinx 12-bit address to the Altera 7-bit address, you can follow these steps:
- Determine the maximum memory address that the Xilinx device can access. This information should be available in the device datasheet.
- Identify the memory address range that the Xilinx device is using for the read operation. This will depend on the starting address of the read operation and the length of the read.
- Map the Xilinx memory address range to the corresponding address range in the Altera device. This will depend on the available memory address range in the Altera device.
- Shift the Xilinx address to the right by 5 bits to get the equivalent 7-bit address in the Altera Avalon streaming interface.
For example, suppose that the Xilinx device can access a maximum memory address range of 4GB (2^32 bytes), and the read operation starts at address 0x80000000 and has a length of 0x400 bytes (400h bytes). To map this address range to the Altera device, you can use the following steps:
- Determine the maximum memory address range of the Altera device. Let's say that the Altera device can access a maximum memory address range of 1GB (2^30 bytes).
- Identify the memory address range that the Xilinx device is using for the read operation. In this case, the Xilinx device is reading from address 0x80000000 to address 0x80000400.
- Map the Xilinx memory address range to the corresponding address range in the Altera device. Since the Altera device can only access a maximum memory address range of 1GB, you can map the Xilinx memory address range to the first 1GB of the Altera memory address range. This means that the starting address of the Xilinx memory address range (0x80000000) will map to the starting address of the Altera memory address range (0x00000000).
- Shift the Xilinx address to the right by 5 bits to get the equivalent 7-bit address in the Altera Avalon streaming interface. In this case, the Xilinx address 0x80000000 will map to the Altera address 0x00000000, which is the starting address of the memory block in the Altera device. To get the next address in the memory block, you can increment the Altera address by 1, which will increment the Xilinx address by 32 (2^5).
I hope this helps you to understand how to map the Xilinx 12-bit address to the Altera 7-bit address. However, keep in mind that the specific mapping will depend on the memory address ranges of the Xilinx and Altera devices, and you should consult the device datasheets for more detailed information.