Forum Discussion

pdewanga's avatar
pdewanga
Icon for New Contributor rankNew Contributor
3 years ago

Understanding difference in Altera Avalon streaming & Xilinx PG156 PCI Express completion format

Hi team , I am working on PCI TLP Conversion from Xilinx to Altera, and require some details about the lower address of completion header format. In Altera Avalon streaming follows general PCI ...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel


  • pdewanga's avatar
    pdewanga
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi Wincent,

    Thanks for your suggestion. However, I need more understanding on this.

    I am using Avalon Streaming PCIe IP with the device 1SG10MHN3F74C2LG (10M). Attaching more details of the address bus with read of length 400h. looking at the difference of Xilinx 12-bit address vs Altera 7-bit address I cannot figure it out how to decode this?