Understanding difference in Altera Avalon streaming & Xilinx PG156 PCI Express completion format

Hi,

We do not have the document to translate the code from Xilinx to Altera.

But I lay down some of the suggestion for you to move on (Please noted it just example)

To translate the lower address of an Altera FPGA to an equivalent Xilinx lower address, you can use the following steps:

1. Determine the address range of the Altera FPGA you want to translate. Let's assume it starts at address 0x00000000 and ends at address 0x0000FFFF.
2. Determine the address range of the Xilinx FPGA you want to translate to. Let's assume it starts at address 0x80000000 and ends at address 0x8000FFFF.
3. Calculate the offset between the two address ranges by subtracting the starting address of the Altera FPGA from the starting address of the Xilinx FPGA. In this case, the offset is 0x80000000 - 0x00000000 = 0x80000000.
4. To translate a specific address in the Altera FPGA to an equivalent address in the Xilinx FPGA, add the offset to the address. For example, to translate address 0x00000123 in the Altera FPGA to an equivalent address in the Xilinx FPGA, you would add the offset and get 0x80000123.

Here is a simple pseudo code to perform this translation:

// Define address ranges

Altera_start = 0x00000000;

Altera_end = 0x0000FFFF;

Xilinx_start = 0x80000000;

Xilinx_end = 0x8000FFFF;

// Calculate offset

offset = Xilinx_start - Altera_start;

// Translate address

Altera_address = 0x00000123;

Xilinx_address = Altera_address + offset;

// Print translated address

print "Translated address: " + Xilinx_address;

Note that this is a simple example and the translation process may be more complex for larger address ranges or more complex FPGA architectures. User might put additional support on this. Hope this is able to help you.

Regards,

Wincent_Intel