New Contributor
Regular ContributorHi,
Yes, there is a functional difference in the address field between Xilinx and Altera in terms of the number of bits used for the lower address. Xilinx uses a 12-bit lower address field while Altera uses a 7-bit lower address field, both of which are compliant with the PCI specification.
When mapping the address field between Xilinx and Altera, you need to take into account the difference in the number of bits used for the lower address. For example, if you are using a Xilinx device that has a 12-bit lower address field to communicate with an Altera device that has a 7-bit lower address field, you need to shift the address bits to match the Altera device's address format.
To map the field accurately, you should consult the documentation provided by both Xilinx and Altera for their respective devices. The documentation will specify how to map the address fields between the devices and what the bit mappings should be. You may also need to consult the PCI specification to ensure that the mappings are compliant with the standard.
Hope this answer your question.
Regards,
Wincent_Intel
New ContributorHi Wincent_Intel,
Thanks for your reply. We have gone with the documents both from Xilinx and Altera, the real question is how to map this lower address. Can you briefly explain and help us with any pseudo code such that the lower address of altera is translated to Xilinx lower address?
We have gone through the document but lagging in understanding it.
Regards,
Piyush
