Honored Contributor
Honored ContributorVHDL code is not a sequential program which a cpu is supposed to execute, so a while loop makes no sense.
VHDL is rather a description language: you are supposed to 'describe' logic gate connections. Any VHDL code which is not convertible (we call this 'synthesizable') in terms of logic gates, signals and flip-flops will not work and can not work. As you pointed out, a while loop is good only for a test bench and simulation, where you actually need to generate artificially some sequential input states. VHDL Usually a comparator is conveniently described in VHDL with high level operators > and <. If you want to follow your 'bare metal' approach, you can use the 'generate' statement, like in the following example: http://fpgacenter.com/digit_dsgn/log_gates/comparator.php
