Unconstrained ports, port paths - what to do with them?

But it is strange still. When i use basic constraints from:

http://www.altera.com/support/examples/timequest/exm-tq-basic-sdc-template.html

=============================================

# Constrain clock port clk with a 10-ns requirement

create_clock -name {TS_clk} -period 10 [get_ports {clk}]

# Automatically apply a generate clock on the output of phase-locked loops (PLLs)

# derive_pll_clocks

# This command can be safely left in the SDC even if no PLLs exist in the design

derive_clock_uncertainty

# Constrain the input I/O path

set_input_delay -clock {TS_clk} -max 3 [all_inputs]

set_input_delay -clock {TS_clk} -min 2 [all_inputs]

# Constrain the output I/O path

set_output_delay -clock {TS_clk} 2 [all_outputs]

=======================================

I am not able to increase fmax up to 120MHz.

But when i dont use constrains for input output, i achieve nearly 200MHz.

You can see my 2 designs. The differences are only in sdc file .... and the differences of fmax is massive.

How it is possible ? How can i increase fmax, when i use constrains to all inputs and outputs ?

Thank you.

Jan