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Hi KxAlpha,
please, could you repair the links:
http://www.altera.com/education/trai...urses/omem1120 It write me, that the page not found and i solve now the same problem unconstrained ports, Input / Output port paths .
Thank you very much.
Jan
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Hi Jan,
I do not know if these are the same tutorials I originally mentioned and I hope there not, since those left still a lot of open questions when you look at your own designs, but here you go:
http://www.altera.com/education/training/courses/ocss1000 http://www.altera.com/education/training/courses/oddr1000 A full list of all the other tutorials can be found here:
http://www.altera.com/servlets/searchcourse?num=188&start=0&total=188&showall=1&coursetype=online You simply need to register for them in order to start them, but they're free to use.
It really is kind of sad, that there are still no decent GUI based constraining wizards around that'll allow you to make the constraints, as it really is hard to keep track of all the formulas. Yeah you can use the input forms for constraints, but what I mean is a graphical representation of an external source/sink and my FPGA where you put in the delay for each part of the equation and get a better feel for what is really important. I really never use the formulas given to their full extent, but instead use some values I feel should work and usually that works OK. The most important thing to have is input and output delay constraints for all I/Os even if you set them to min/max 0, at least this way Quartus will know to what clock those signals are related to. That solves almost all of those works after every second compile even without me changing anything problems. After that a few multicycles where applicable and even if you get tons of warnings, your compilation results will almost always remain the same (if the design itself is working in silicon).
Honored Contributor
