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Altera_Forum's avatar
Altera_Forum
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15 years ago

Unconstrained Paths errors

Hi all, I'm having problems with my design Cyclone III with MT48LC4M32B2-7 sdram. I'm new to TimeQuest Analyzer, Clock Phase Shift settings, or Tco, Tpd. Hope someone could help me out to po...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi,

I'm using SDR MT48LC4M32B2-7 memory with Cyclone III. In SOPC Builder, I select SDRAM Controller and default to Micron MT48LC4M32B2-7. For my system clock, I pick 50mhz and same with SDRAM clock in PLL.

Now, the phase shift that I already tried -3.5ns, -3.0ns, -2.0ns , -72deg.... but no luck.

Thanks,

Sean