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Altera_Forum's avatar
Altera_Forum
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9 years ago

Unable to synthesize the design with Macros and header files due to undefined Macros

Hi, I have a design with some Macros and these are being used in multiple files. These Macros are defined in the header file <Macro_defs>.vh. I have added the <Macro_defs>.vh file in my Quartus...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I think it just adds the file to the project. It doesn't treat it in any special way, like making it a global or anything like that. I think it's for when users create a file with a .inc extension, and want it to be added/read as a Verilog file, which used to be pretty common. (Now I see users doing more of <name>_pkg.sv)