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Altera_Forum
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9 years ago

Unable to synthesize the design with Macros and header files due to undefined Macros

Hi, I have a design with some Macros and these are being used in multiple files. These Macros are defined in the header file <Macro_defs>.vh. I have added the <Macro_defs>.vh file in my Quartus...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hello Rysc,

Thank you very much for the explanation.

What exactly is the purpose of "VERILOG_INCLUDE_FILE" then? It doesn't seem to work at all. I do not find much information on this anywhere?