Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorUnable to synthesize the design with Macros and header files due to undefined Macros
Hi, I have a design with some Macros and these are being used in multiple files. These Macros are defined in the header file <Macro_defs>.vh. I have added the <Macro_defs>.vh file in my Quartus...
Altera_ForumHonored Contributor
Honored ContributorAnd I think users would name a file that was included "somename.inc", which didn't really indicate it was Verilog. I'm guessing that's what the assignment was used for, to add it as Verilog.
