Forum Discussion

Abhishek_C_Intel's avatar
Abhishek_C_Intel
Icon for New Contributor rankNew Contributor
7 years ago

Unable to synthesis design if defines are included in seperate file

I am synthesizing my design in quartus prime. The FPGA used in our design is stratix 10. I am synthesis a synopsys designware IP. The IP has separate files for defines and these defines were saved as...
SAR's avatar
SAR
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hi,

You can take a look at the opencores design that I used for the above two methods. The original design has the include file with extension .inc and I’ve modified it with extension .v and have quartus compile the design.