Unable to synthesis design if defines are included in seperate file

Hi,

I just synthesized a design with an include file with extension .inc and it works fine. You can use the following line in the projects QSF file:

set_global_assignment -name INCLUDE_FILE <path_to_file>

or

set_global_assignment –name VERILOG_FILE <path_to_file> (if the file has extension .v)

and not

set_global_assignment –name VERILOG_INCLUDE_FILE < >

The path has to be absolute (full path) and not relative (../../../..) . Save the QSF file and then rerun the synthesis. The user can also try placing the include file in the same folder as the rest of the RTL source files.

If you are doing so via the Quartus GUI, then add the include files into the project via Project -> Add / Remove Source files option. This is equivalent to the set_global_assignment –name INCLUDE_FILE statement and will make sure the include files are taken into consideration for synthesis and rest of the flow.

If the include file has the .v extension, then use the

set_global_assignment –name VERILOG_FILE <> statement in the QSF file ad include it as a regular Verilog file.