Unable to synthesis design if defines are included in seperate file

Hi, Thank you for your response. My question is I am having two files which contains `define and the other files which are using it. In my file list I have maintained the order of files so that files containing `defines are read first. Still quartus is generating an error. I am not facing this issue with any other synthesis tool like Xilinx vivado or synplifypro etc. I checked the switches/options for set_global_assignment and found that we can use VERILOG_INCLUDE_FILE switch/option. Yet the tool is generating the error. I think this issue is only related to quartus. Is there a way to avoid manually editing the files and use options/switches available with set_gobal_assignment. Thanks & Regards Abhishek