Unable to synthesis design if defines are included in seperate file

Hi,

You can refer simple example below.

----------------------------------------------

and_op.v

-----------------------------------------------

module and_op (a, b, c);

`include "macro.v"

output a;

input b, c;

`ifdef behavioral

wire a = b & c;

`else

or a1 (a,b,c);

`endif

endmodule

--------------------------------------------------

macro.v

--------------------------------------------------

`define behavioral

--------------------------------------------------

Refer below link for more information

Intel Quartus Prime Integrated Synthesis of https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/qts/qts-qps-5v1.pdf

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd07231998_9862.html

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)