Altera_Forum
Honored Contributor
Honored ContributorUnable to run simulation in Simulation Waveform Editor
Hello, I'm just starting to use Quartus for VHDL designs and I keep running into a problem while trying to run a simulation using a .vwf file in the Simulation Waveform Editor. Whenever my design infers a higher level component (such as the altsyncram in my example), I am unable to run a functional or a timing simulation without receiving the following error:
--- Quote Start --- # ** Error: (vsim-3033) nofile(37): Instantiation of 'generic_m10k' failed. The design unit was not found.# # Region: /sim_tester_vlg_vec_tst/i1/\ram_rtl_0|auto_generated|ram_block1a0 # Searched libraries:# C:/altera/13.1/modelsim_ase/altera/verilog/cyclonev# C:/altera/13.1/modelsim_ase/altera/verilog/altera# C:/altera/13.1/modelsim_ase/altera/verilog/altera_mf# C:/altera/13.1/modelsim_ase/altera/verilog/220model# C:/altera/13.1/modelsim_ase/altera/vhdl/sgate# C:/altera/13.1/modelsim_ase/altera/verilog/cyclonev# Loading work.sim_tester_vlg_sample_tst# Loading work.sim_tester_vlg_check_tst# Error loading design Error loading design Error. --- Quote End --- I wrote some simple code to use to try to figure this error out. The VHDL code I am using is as follows:library IEEE;
use IEEE.std_logic_1164.all;
entity sim_tester is
port(in1: in std_logic_vector(7 downto 0); clk, r_en, w_en: in std_logic;
out1: out std_logic_vector(7 downto 0));
end sim_tester;
architecture sim of sim_tester is
type MemoryType is array(0 to 15) of std_logic_vector(7 downto 0);
signal ram: MemoryType := (others => (others => '0'));
signal w_addr: integer range 0 to 15 := 0;
signal r_addr: integer range 0 to 15 := 0;
begin
process(clk)
begin
if clk'event and clk = '1' then
if r_en = '1' then
out1 <= ram(r_addr);
elsif w_en = '1' then
ram(w_addr) <= in1;
end if;
end if;
end process;
end sim;
