Forum Discussion
Altera_Forum
Honored Contributor
14 years agoyou need to convert the schematic to verilog or VHDL before you can simulate it. You can do it via the file menu:
file -> create/update -> create HDL from current file.you need to convert the schematic to verilog or VHDL before you can simulate it. You can do it via the file menu:
file -> create/update -> create HDL from current file.