Uart

My project is to test the digital circuit(hardware verification). I have attached a picture of overview of this project and UART_comm simulation waveform. In the waveform, the data_in is the data going the be shifted out.

If there is any info wanted, just let me know. Thanks for ur reply.

Just to add in, the led is on(serial_out) all the time when i assign the serial_out to the led. Before i program, there is voltage across the receive pin. However, when i assign it to transmit pin and program it, there is no voltage across the transmit and receive pin.

For your info, the serial_out is active low.

hello jasonkee111,

I have played around with your code and have now a working solution.

Configure your hyperterminal as follows:

Baudrate/s: 9600

Databits: 8

Parity: none

Stopbits: 1

Flow-Control: none

It is not working perfect, means it now continously sends the last char wich you put into TXD_DATA.

regards,

Alex

@ spellic (http://www.alteraforum.com/forum/member.php?u=11333)

Hi

could you please explain why division numbers are different for TX and RX in clk_generator module as both of thm are working on same baud rate?

module Baud_Counter (

// Inputs

input clk,

input reset,

input reset_counters,

// Outputs

output reg baud_clock_rising_edge,

output reg baud_clock_falling_edge,

output reg all_bits_transmitted

);

parameter BAUD_COUNTER_WIDTH = 9;

parameter BAUD_COUNT = 5;

parameter BAUD_TICK_COUNT = BAUD_COUNT - 1; //9'd433;

parameter HALF_BAUD_TICK_COUNT = BAUD_COUNT / 2; //9'd216;

parameter DATA_WIDTH = 9;

parameter TOTAL_DATA_WIDTH = DATA_WIDTH + 2;

reg [(BAUD_COUNTER_WIDTH - 1):0] baud_counter;

reg [3:0] bit_counter;

// control baud_counter

always @(posedge clk)

begin

if (reset == 1'b1)

baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}};

else if (reset_counters)

baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}};

else if (baud_counter == BAUD_TICK_COUNT)

baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}};

else

baud_counter <= baud_counter + 1'b1;

end

// control baud_clock_rising_edge signal

always @(posedge clk)

begin

if (reset == 1'b1)

baud_clock_rising_edge <= 1'b0;

else if (baud_counter == BAUD_TICK_COUNT)

baud_clock_rising_edge <= 1'b1;

else

baud_clock_rising_edge <= 1'b0;

end

// control baud_clock_falling_edge signal

always @(posedge clk)

begin

if (reset == 1'b1)

baud_clock_falling_edge <= 1'b0;

else if (baud_counter == HALF_BAUD_TICK_COUNT)

baud_clock_falling_edge <= 1'b1;

else

baud_clock_falling_edge <= 1'b0;

end

// control bit counter

always @(posedge clk)

begin

if (reset == 1'b1)

bit_counter <= 4'h0;

else if (reset_counters)

bit_counter <= 4'h0;

else if (bit_counter == TOTAL_DATA_WIDTH)

bit_counter <= 4'h0;

else if (baud_counter == BAUD_TICK_COUNT)

bit_counter <= bit_counter + 4'h1;

end

// control all_bits_transmitted signal

always @(posedge clk)

begin

if (reset == 1'b1)

all_bits_transmitted <= 1'b0;

else if (bit_counter == TOTAL_DATA_WIDTH)

all_bits_transmitted <= 1'b1;

else

all_bits_transmitted <= 1'b0;

end

endmodule

module RS232_In (

// Inputs

input clk,

input reset,

input serial_data_in,

input receive_data_en,

// Outputs

output reg [(DATA_WIDTH-1):0] received_data,

output reg receiving_data,

output reg data_received,

output baud_clock

);

parameter BAUD_COUNT = 9'd434;

parameter DATA_WIDTH = 8;

parameter TOTAL_DATA_WIDTH = DATA_WIDTH + 2;

wire shift_data_reg_en;

wire all_bits_received;

assign baud_clock = shift_data_reg_en;

reg [(TOTAL_DATA_WIDTH - 1):0] data_in_shift_reg;

//reg receiving_data;

reg prev_receiving_data;

always @(posedge clk)

begin

if (reset == 1'b1)

receiving_data <= 1'b0;

else if (all_bits_received == 1'b1)

receiving_data <= 1'b0;

else if (serial_data_in == 1'b0)

receiving_data <= 1'b1;

end

always @(posedge clk)

begin

prev_receiving_data <= receiving_data;

if (receiving_data==1'b1)

data_received <= 1'b0;

else if (prev_receiving_data==1'b1)

begin

data_received <= 1'b1;

received_data <= data_in_shift_reg[DATA_WIDTH:1];

end

end

always @(posedge clk)

begin

if (reset == 1'b1)

data_in_shift_reg <= {TOTAL_DATA_WIDTH{1'b0}};

else if (shift_data_reg_en)

data_in_shift_reg <=

{serial_data_in, data_in_shift_reg[(TOTAL_DATA_WIDTH - 1):1]};

end

Baud_Counter RS232_In_Counter (

// Inputs

.clk(clk),

.reset(reset),

.reset_counters(~receiving_data),

// Outputs

.baud_clock_rising_edge(),

.baud_clock_falling_edge(shift_data_reg_en),

.all_bits_transmitted(all_bits_received)

);

defparam

RS232_In_Counter.BAUD_COUNT= BAUD_COUNT,

RS232_In_Counter.DATA_WIDTH= DATA_WIDTH;

/*

Altera_UP_SYNC_FIFO RS232_In_FIFO (

// Inputs

.clk (clk),

.reset (reset),

.write_en (all_bits_received & ~fifo_is_full),

.write_data (data_in_shift_reg[(DATA_WIDTH + 1):1]),

.read_en (receive_data_en & ~fifo_is_empty),

// Bidirectionals

// Outputs

.fifo_is_empty (fifo_is_empty),

.fifo_is_full (fifo_is_full),

.words_used (fifo_used),

.read_data (received_data)

);

defparam

RS232_In_FIFO.DATA_WIDTH = DATA_WIDTH,

RS232_In_FIFO.DATA_DEPTH = 128,

RS232_In_FIFO.ADDR_WIDTH = 7;

*/

endmodule

module rs232lab(input CLOCK_50, input UART_RXD, inout[7:0] received_data,input [3:0] KEY,output [8:0] LEDG);

parameter DATA_WIDTH = 8;

//reg [DATA_WIDTH-1:0] received_data;

wire RST;

assign RST = KEY[0];

wire reset = ~RST;

wire receiving_data, data_received;

assign LEDG[3] = data_received;

assign LEDG[6] = receiving_data;

RS232_In u3(

// Inputs

.clk(CLOCK_50),

.reset(reset),

.serial_data_in(UART_RXD), // UART_RXD

.receive_data_en(1'b1),

// Outputs

.received_data(received_data),

.data_received(data_received),

.receiving_data(receiving_data)

);

endmodule

can anyone tell me where is my code wrong?

Maybe you could describe the problem you have first?

Which hardware do you use?

Is this the complete source of your project? Everything in one file?

Sohail.nadian

hello can i ask you , do u have now the right code i need it pliz .........

and can you briefly describe what your code do ??? pliz i need it for my project....