Thank You Richard, the doc confirms that there is no typical case analysis and it is englobed in "everything in between fast and slow corners".
Some useful info in the doc as well answering some of my questions (like the low/high user voltage taken into account for slow/fast).
I will do a test with a speed grade +1 faster (speed 6) to see the impact on the slow analysis,
Edit: I cannot, there is only one speed grade for industrial: Industrial grade devices are offered in the –I7 speed grade.
https://www.intel.com/content/www/us/en/docs/programmable/683801/current/cyclone-v-device-datasheet.html
For example, the routing interconnect delays cannot
be modeled with a simple static value or even a table of
values because there are too many independent electrical
parameters leading to too many configurations. The
capacitive loading, its distribution along the wire, the listening
position, the varying RC as the wire goes through several
metal layers, and the input waveform supplied to any of the
interconnect wires are all determined by the place and route
engine, leading to a wide range of electrical configurations.
Uncetainties:
• Manufacturing process on-die variation
• Rise and fall skew in uncorrelated N- and P-channel
transistor speed
• Clock uncertainty and jitter
• Non-uniform voltage on the power distribution network
(PDN)
• End-of-life degradation effects
• Slight variations in hardware design of equivalent blocks
• Crosstalk
The third aspect of the operating conditions is the relative
speed of each FPGA versus the limit of the speed grade with
which it is marked. This is one aspect that the designer has
no control over. It should also be noted that devices within
one speed grade can still differ slightly in performance,
predominantly due to variation in the manufacturing process.
All devices, however, are guaranteed to be faster than the
limit of the speed grade.
Also, between fast (high voltage) and slow (low voltage), the user voltage supply level are taken into account.
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