Type do not match for port

I have once more question:

I program this code and I've already initial all value but the output zzero, ccy, sometime their value are "U", "1", "0". Their value are "1" and "0" it's Ok but the value is "U", I can not soft it. Could you help me?

VARIABLE A,B,C           :std_logic_vector(15 DOWNTO 0):=(others => '0');
VARIABLE alu_out         :std_logic_vector(15 DOWNTO 0):=(others => '0');
VARIABLE zzero,nneg,ccy  :STD_LOGIC:='0';
constant z :std_logic_vector(15 downto 0) := (others => '0');

procedure alu (zzero,nneg,ccy  :out STD_LOGIC;
               alu_out         :out std_logic_vector(15 DOWNTO 0);
               a,b             :in std_logic_vector(15 DOWNTO 0):=(others => '0');
               alu_op          :in UNSIGNED(2 DOWNTO 0):=(others =>'0')) is
variable alu_out_reg :std_logic_vector(16 DOWNTO 0):=(others => '0');
variable alu_out_or  :std_logic_vector(31 downto 0):=(others => '0');
begin
  case alu_op  is
    when "000" =>     alu_out_reg := ("0" & a) + ("0" & b); ------add
                     alu_out := alu_out_reg(15 downto 0);
                     ccy := alu_out_reg(16);
                     if alu_out_reg(15 downto 0) = z then 
					 zzero := '1';
                     else zzero:= '0';
                     end if;
    when others =>  null;
  end case;  
end  alu;

BEGIN
  A := RF(conv_integer(fld_a));
  B := RF(conv_integer(fld_b));
  if control_con = '0' then
    alu(zzero,nneg,ccy,alu_out,A,B,alu_op);
    zero <= zzero;
    neg <= nneg;
    cy <= ccy;
  end if;

the value of "neg" alway is "U"

Thank you very much