Honored ContributorI am working with alt2gx modul, and I can't understand the conection between the clocks, nad data rate.
If I have 8 bits channel width, and the input clock fo pll is 156MHz, and I want to work at data rate of 780Mbps, Why the tx_clkout frequency is 78MHz and not 97.5MHz (780/8)? Is it because the syncronization bits, the actual frequency of the channel becomes higher?
Honored ContributorThe input clock rate is pretty configurable such that it is endependent of your serial or parallel data rate. What's the parallel data width coming in/out of the module? Are you doing anything that adds/loses data, like 8b10b?
Honored ContributorYes I am using 8 to 10 bit. So the modul gives me the actual rate of the parallel channel that i need to use in order to get the data rate that I choose in the serial channel. Is this the reason why the serial data rate is devided by 10 (since the 8to 10 bit adds 2 more bites)?
I will check the frequency without 8to10 bit, but I should get output frequency of data rate devided by 8, am I right?Honored ContributorYou put in 8 bits of data, 2 more bits are added by 8b10b block, and so 10 bits go through the serializer and out the device. So you do have a 10:1 ratio. (Same thing if being received.) High-speed I/O pretty much always lose some of their throughput for the encoding. (There's a 64/66b encoding, I can't think the name of off the top of my head, that might work better. I also can't remember if it's a hard block, but it would also depend on the device you're using.)
Honored ContributorWell ratio of 64/66 is not critical. I could not understand at the begining why is the data rate devided by 10 and not 8. You explained it. Thanks.
