two counters, two clocks - loop problem!

Thank you for the quick responses!

I did think of using a common process (honest guv'). This is why I mentioned that the two clocks are indeed synchronized.

I did write some VHDL to instantiate this, but I got my knickers in a bit of a twist and as a result the second faster clock was always slightly displaced (in terms of clock periods) from the termination of the first slower clock. It performed perfectly apart from that. Even though I had written the VHDL to do this, trying to then get my head around what I had written to understand this offset caused a headache of massive proportions!

It is true what they say about reading and understanding pre-written VHDL (even your own!).

I did not instantiate my common process approach in the manner that both of you are suggesting though, so I will try again with your very helpful insights in mind.

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Otherwise a request/acknowldege handshake scheme might be used to couple both counters as intended.

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I believe (but don't quote me) that is also something I have seen on the internet that can be used to solve cross clocking domain problems? As I understood it a kind of inter-process tracking latch. So not one to give up I tried that too: 5 attempts later, quite clearly I still did not quite understand how to do this... and hence this forum post. For the record then, how would one instantiate this kind of process? Personally it would be really interesting to know how this is done. At the end of the day what I am asking is how to train my brain to think in a certain way about such VHDL 'nasties'.

Thank you again,

Andy