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The two clocks are synchronized:
A clock (used to drive the fast counter above) drives another counter which when that hits a certain count resets back to zero and carries on counting. When it resets this is the clock source that drives the first slower counter above.
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Generating a slow clock this way makes it difficult to drive signals from the fast to the slow clock domain.
Instead you'd prefer a single clock domain solution where a slow clock tick is used as a clock enable in the slow counter. Building the design this way allows to operate both counters in one process and sharing all signals between both counters, the straightforward way.
Otherwise a request/acknowldege handshake scheme might be used to couple both counters as intended.
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