Two Clock Inputs questions for VHDL

It looks like you have created an XOR gate. (Z <= CPIN XOR CPINH;) I'm not sure if this is the desired behavior.

If your initial description is correct, I agree with Tricky - use a master clock to synchronize your behavior. Something like:

PROCESS(CLK, RESET)
BEGIN
  IF (RESET = '1') THEN
    cpin_reg_s <= '0';
    cpinh_reg_s <= '0';
    cpin_reg1_s <= '0';
    cpinh_reg1_s <= '0';
  ELSIF (rising_edge(CLK)) THEN
    --register your inputs to prevent timing issues
    cpin_reg_s <= CPIN;
    cpinh_reg_s <= CPINH;
    --remember what last register states were
    cpin_reg1_s <= cpin_reg_s;
    cpinh_reg1_s <= cpinh_reg_s;
    --make decision to do stuff
      Z <= (cpin_reg_s AND (NOT cpin_reg1_s)  AND (NOT cpinh_reg_s)) OR (cpinh_reg_s AND (NOT cpinh_reg1_s) AND (NOT cpin_reg_s));
    END IF;
  END IF;
END PROCESS;

Be sure that your clock is significantly faster than your maximum input transition rate.