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Altera_Forum
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13 years ago

Two Clock Inputs questions for VHDL

I have a process that needs to be run off two clocks (shifting Bits) When clk1 changes state and clk2 is low i should shift ALSO when clk2 changes state and clk1 is low i should shift. I am hav...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

basically, you cannot use two clocks in FPGAs (nothing wrong with it in VHDL, but it doesnt map to any real hardware).

I suggest you run a master clock and synchronise everything to it.