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This is quite the ugly problem. I think more information is needed to recommend how to help.
CPIN and CPINH:
Are these clocked inputs?
What is the maximum toggle rate of your inputs?
Do you have any actual clocks available in your design? If so, what speed(s)?
If both CPIN and CPINH have the same maximum toggle rate, is the phase relationship between the two known?
Side note:
"Z <= X XOR Y;" does not need to be wrapped in a process. It can stand alone and will generate as you would expect.
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CPIn and CPINH are controlled by debounced switches, this is for a lab project and i am trying to figure out this last part i need to figure out.
so if i clock cpin and cpinh is low then it shifts.....
so if i clock cpinh and cpin is low then it shifts..... this shifting is controlled by a process that runs off when Z changes states
the xor is there for
when CPin changes it controls X
when CPinh changes it controls y
if X and Y are 0 nothing happens
if X and Y are 10 or 01 shift -- this is why the XOR is needed generates a one on both of these conditions
if X and Y are 11 or 11 nothing happens
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