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Altera_Forum's avatar
Altera_Forum
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13 years ago

Two Clock Inputs questions for VHDL

I have a process that needs to be run off two clocks (shifting Bits) When clk1 changes state and clk2 is low i should shift ALSO when clk2 changes state and clk1 is low i should shift. I am hav...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

This is quite the ugly problem. I think more information is needed to recommend how to help.

CPIN and CPINH:

Are these clocked inputs?

What is the maximum toggle rate of your inputs?

Do you have any actual clocks available in your design? If so, what speed(s)?

If both CPIN and CPINH have the same maximum toggle rate, is the phase relationship between the two known?

Side note:

"Z <= X XOR Y;" does not need to be wrapped in a process. It can stand alone and will generate as you would expect.