Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Turn off enable_advanced_io_timing for Arria II GX?

I got forced into an Arria II GX due to lack of resources in an Arria GX. I was, with the Arria GX, able to assign the pin loading for each pin in my SO-DIMM interface. The Arria II GX forces me to do a more complex loading analysis for the pins in my SO-DIMM interface because individual pin capacitance assignments are not available - the enable_advanced_io_timing timequest setting is forced on and can't be turned off via the GUI - see attached screenshot.

Is there any way to turn off enable_advanced_io_timing so i still can use the simpler capacitive loading model? Is this safe for the Arria II GX?

I'm designing a 200 MHz SO-DIMM interface. Since a capacitive loading model was good enough for the Arria GX, it should be good enough for the Arria II GX at the same SO-DIMM clock speed?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Okay, I have figured out that I can add in the far-end load capacitance per pin for my SO-DIMM interface. Once I have the actual distributed L/C of the traces (from Hyperlynx after layout) I will update the board trace models in the pin planner.

    I am however not quite clear how the near-end pin capacitance is modeled. My bidir DQ pins are shown in the board trace model edit screen as output pins (see attached screen shot). Should I just add the Arria II DQ pin capacitance in the Cn text box and ignore that the graphics shows the driver/receiver in the wrong direction?

    Thanks.